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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. 19-5138; rev 4; 1/12 /v denotes an automotive qualified part. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. t = tape and reel. ordering information general description the max9249 serializer with lvds system interface utilizes maxims gigabit multimedia serial link (gmsl) technology. the max9249 serializer pairs with any gmsl deserializer to form a complete digital serial link for joint transmission of high-speed video, audio, and control data. the max9249 allows a maximum serial payload data rate of 2.5gbps for a 15m shielded twisted-pair (stp) cable. the serializer operates up to a maximum clock rate of 104mhz (3-channel lvds) or 78mhz (4-channel lvds). this serial link supports display panels from qvga (320 x 240) to wxga (1280 x 800) and higher with 24-bit color. the 3-channel mode handles three lanes of lvds data (21 bits), uart control signals, and three audio signals. the 4-channel mode handles four lanes of lvds data (28 bits), uart control signals, three audio signals, and/or up to three auxiliary parallel inputs. the three audio inputs form a standard i 2 s interface, supporting sample rates from 8khz to 192khz and audio word lengths of 4 to 32 bits. the embedded control chan - nel forms a full-duplex, differential, 100kbps to 1mbps uart link between the serializer and deserializer. the electronic control unit (ecu), or microcontroller ( f c), can be located on the max9249 side of the link (typical for video display), on the deserializer side of the link (typi - cal for image sensing), or on both sides. in addition, the control channel enables ecu/ f c control of peripherals on the remote side, such as backlight control, grayscale gamma correction, camera module, and touch screen. base-mode communication with peripherals uses either i 2 c or the gmsl uart format. a bypass mode enables full-duplex communication using custom uart formats. the max9249 serializer driver preemphasis, along with the channel equalizer on the gmsl deserializer, extends the link length and enhances the link reliability. spread spectrum is available on the max9249 to reduce emi on the serial link and the parallel output of the gmsl dese - rializer. the serial output complies with iso 10605 and iec 61000-4-2 esd protection standards. the core supply for the max9249 is 1.8v. the i/o supply ranges from 1.8v to 3.3v. the max9249 is available in a 48-pin tqfp package (7mm x 7mm) with an exposed pad. electrical performance is guaranteed over the -40 n c to +105 n c automotive temperature range. features s pairs with any gmsl deserializer s 2.5gbps payload rate ac-coupled serial link with 8b/10b line coding s supports up to wxga (1280 x 800) with 24-bit color s 8.33mhz to 104mhz (3-channel lvds) or 6.25mhz to 78mhz (4-channel lvds) input clock s 4-bit to 32-bit word length, 8khz to 192khz i 2 s audio channel supports high-definition audio s embedded half-/full-duplex bidirectional control channel (100kbps to 1mbps) s interrupt supports touch-screen functions for display panels s remote-end i 2 c master for peripherals s preemphasis line driver s programmable spread spectrum on the serial outputs for reduced emi s automatic data-rate detection allows on-the- fly data-rate change s input clock pll jitter attenuator s built-in prbs generator for ber testing of the serial link s line-fault detector detects serial link shorts to ground, battery, or open link s iso 10605 and iec 61000-4-2 esd protection s -40 n c to +105 n c operating temperature range s 1.8v to 3.3v i/o, 1.8v core, and 3.3v lvds supplies s patent pending applications high-resolution automotive navigation rear-seat infotainment megapixel camera systems evaluation kit available part temp range pin-package max9249gcm/v+ -40 n c to +105 n c 48 tqfp-ep* max9249gcm/v+t -40 n c to +105 n c 48 tqfp-ep* max9249 gigabit multimedia serial link serializer with lvds system interface
2 ______________________________________________________________________________________ stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. avdd to agnd .................................................... -0.5v to +1.9v lvdsvdd to agnd .............................................. -0.5v to +3.9v dvdd to gnd ...................................................... -0.5v to +1.9v iovdd to gnd ..................................................... -0.5v to +3.9v any ground to any ground ................................. -0.5v to +0.5v rxin_ _, rxclkin_ to agnd .............................. -0.5v to +3.9v out+, out- to agnd ......................................... -0.5v to +1.9v lmn_ to agnd (15ma current limit) .................... -0.5v to +3.9v all other pins to any ground .............. -0.5v to (v iovdd + 0.5v) out+, out- short circuit to ground or supply ....... continuous continuous power dissipation ( t a = +70 n c) 48-pin tqfp (derate 36.2mw/ n c above +70 n c) .... 2898.6mw esd protection human body model (r d = 1.5k, c s = 100pf) (rxin_ _, rxclkin_, out+, out-) to agnd ................ 8kv all other pins to gnd ...................................................... 3kv iec 61000-4-2 (r d = 330, c s = 150pf) contact discharge (rxin_ _, rxclkin_) to agnd ....................................... 4kv (out+, out-) to agnd ................................................ 10kv air discharge (rxin_ _, rxclkin_) to agnd ....................................... 8kv (out+, out-) to agnd ................................................ 12kv iso 10605 (r d = 2k, c s = 330pf) contact discharge (rxin_ _, rxclkin_) to agnd ....................................... 6kv (out+, out-) to agnd ................................................ 10kv air discharge (rxin_ _, rxclkin_) to agnd ..................................... 20kv (out+, out-) to agnd ................................................ 30kv operating temperature range ........................ -40 n c to +105 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c dc electrical characteristics (v dvdd = v avdd = 1.7v to 1.9v, v lvdsvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 i 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. differential input voltage |v id | = 0.1v to 1.2v, input common-mode voltage v cm = |v id /2| to 2.4v - |v id /2|. typical values are at v dvdd = v avdd = v iovdd = 1.8v, v lvdsvdd = 3.3v, t a = +25 n c.) absolute maximum ratings package thermal characteristics (note 1) 48 tqfp-ep junction-to-ambient thermal resistance ( ja ) ....... 27.6 n c/w junction-to-case thermal resistance ( jc ) ................. 2 n c/w note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . parameter symbol conditions min typ max units single-ended inputs ( pwdn , ssen, bws, drs, ms, cds, autos , sd/cntl0, sck, ws, cntl_) high-level input voltage v ih1 pwdn , ssen, bws, drs, ms, cds, autos 0.65 x v iovdd v sd/cntl0, sck, ws, cntl_ 0.7 x v iovdd low-level input voltage v il1 0.35 x v iovdd v input current i in1 v in = 0 to v iovdd -10 +10 f a input clamp voltage v cl i cl = -18ma -1.5 v single-ended output (int) high-level output voltage v oh1 i oh = -2ma v iovdd - 0.2 v low-level output voltage v ol1 i ol = 2ma 0.2 v output short-circuit current i os v o = 0v v iovdd = 3.0v to 3.6v 16 35 64 ma v iovdd = 1.7v to 1.9v 3 12 21 max9249 gigabit multimedia serial link serializer with lvds system interface
_______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v dvdd = v avdd = 1.7v to 1.9v, v lvdsvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 i 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. differential input voltage |v id | = 0.1v to 1.2v, input common-mode voltage v cm = |v id /2| to 2.4v - |v id /2|. typical values are at v dvdd = v avdd = v iovdd = 1.8v, v lvdsvdd = 3.3v, t a = +25 n c.) parameter symbol conditions min typ max units i 2 c and uart i/o, open-drain output (rx/sda, tx/scl, lflt ) high-level input voltage v ih2 0.7 x v iovdd v low-level input voltage v il2 0.3 x v iovdd v input current i in2 v in = 0 to v iovdd (note 2) -110 +5 f a low-level open-drain output voltage v ol2 i ol = 3ma v iovdd = 1.7v to 1.9v 0.4 v v iovdd = 3.0v to 3.6v 0.3 differential output (out+, out-) differential output voltage v od preemphasis off (figure 1) 300 400 500 mv 3.3db preemphasis setting, v od(p) (figure 2) 350 610 3.3db deemphasis setting, v od(d) (figure 2) 240 425 change in v od between complementary output states d v od 15 mv output offset voltage (v out+ + v out- )/2 = v os v os preemphasis off 1.1 1.4 1.56 v change in v os between complementary output states d v os 15 mv output short-circuit current i os v out+ or v out- = 0v -60 ma v out+ or v out- = 1.9v 25 magnitude of differential output short-circuit current i osd v od = 0v 25 ma output termination resistance (internal) r o from out+, out- to v avdd 45 54 63 i reverse control-channel receiver (out+, out-) high switching threshold v chr 27 mv low switching threshold v clr -27 mv line-fault detection input (lmn_) short-to-gnd threshold v tg figure 3 0.3 v normal thresholds v tn figure 3 0.57 1.07 v open thresholds v to figure 3 1.45 v io + 60mv v open input voltage v io figure 3 1.47 1.75 v short-to-battery threshold v te figure 3 2.47 lvds inputs (rxin_ _, rxclkin_) differential input high threshold v th 50 mv differential input low threshold v tl -50 mv max9249 gigabit multimedia serial link serializer with lvds system interface
4 ______________________________________________________________________________________ dc electrical characteristics (continued) (v dvdd = v avdd = 1.7v to 1.9v, v lvdsvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 i 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. differential input voltage |v id | = 0.1v to 1.2v, input common-mode voltage v cm = |v id /2| to 2.4v - |v id /2|. typical values are at v dvdd = v avdd = v iovdd = 1.8v, v lvdsvdd = 3.3v, t a = +25 n c.) ac electrical characteristics (v dvdd = v avdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 i 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. differential input voltage |v id | = 0.15v to 1.2v, input common-mode voltage v cm = |v id /2| to 2.4v - |v id /2|. typical values are at v dvdd = v avdd = v iovdd = 1.8v, v lvdsvdd = 3.3v, t a = +25 n c.) parameter symbol conditions min typ max units input differential termination resistance r term 85 110 135 i input current i in+ , i in- pwdn = high or low, in+ and in- are shorted -25 +25 f a power-off input current i in0+ , i in0- v avdd = v dvdd = v iovdd = 0v -40 +40 f a power supply worst-case supply current (figure 4) i wcs bws = gnd f rxclkin_ = 16.6mhz 125 165 ma f rxclkin_ = 33.3mhz 135 175 f rxclkin_ = 66.6mhz 150 190 f rxclkin_ = 104mhz 175 220 sleep-mode supply current i ccs lvds inputs are not driven 45 125 f a power-down supply current i ccz pwdn = gnd, lvds inputs are not driven 5 80 f a parameter symbol conditions min typ max units clock input (rxclkin_) clock frequency f rxclkin_ bws = gnd, v drs = v iovdd 8.33 16.66 mhz bws = gnd, drs = gnd 16.66 104 v bws = v iovdd , v drs = v iovdd 6.25 12.5 v bws = v iovdd , drs = gnd 12.5 78 i 2 c/uart port timing (note 3) output rise time t r 30% to 70%, c l = 10pf to 100pf, 1k i pullup to iovdd 20 150 ns output fall time t f 70% to 30%, c l = 10pf to 100pf, 1k i pullup to iovdd 20 150 ns input setup time t set i 2 c only (figure 5) 100 ns input hold time t hold i 2 c only (figure 5) 0 ns switching characteristics (note 3) differential output rise/fall time t r , t f 20% to 80%, v od 400mv, r l = 100 i , serial-bit rate = 3.125gbps (note 3) 90 150 ps total serial output jitter t tsoj1 3.125gbps prbs signal, measured at v od = 0v differential, preemphasis disabled (figure 6) 0.25 ui deterministic serial output jitter t dsoj2 3.125gbps prbs signal 0.15 ui cntl_ input setup time t set cntl_ (figure 7) 3 ns cntl_ input hold time t hold cntl_ (figure 7) 1.5 ns rxin_ _ skew margin t rskm figure 8 0.3 ui max9249 gigabit multimedia serial link serializer with lvds system interface
_______________________________________________________________________________________ 5 ac electrical characteristics (continued) (v dvdd = v avdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 i 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. differential input voltage |v id | = 0.15v to 1.2v, input common-mode voltage v cm = |v id /2| to 2.4v - |v id /2|. typical values are at v dvdd = v avdd = v iovdd = 1.8v, v lvdsvdd = 3.3v, t a = +25 n c.) note 2: minimum i in due to voltage drop across the internal pullup resistor. note 3: not production tested. note 4: iovdd rxclkin_ rxclkin_ 11 bit time (bws 0), (bws v ) 30 f 40 f = = = = parameter symbol conditions min typ max units serializer delay (note 4) t sd figure 9 spread spectrum enabled 2950 bits spread spectrum disabled 390 link start time t lock figure 10 3.5 ms power-up time t pu figure 11 3.5 ms i 2 s input timing ws frequency f ws table 3 8 192 khz sample word length n ws table 3 4 32 bits sck frequency f sck f sck = f ws x n ws x 2 (8 x 4) x 2 (192 x 32) x 2 khz sck clock high time (note 3) t hc v sck r v ih , t sck = 1/f sck 0.35 x t sck ns sck clock low time (note 3) t lc v sck v il , t sck = 1/f sck 0.35 x t sck ns sd/cntl0, ws setup time t set figure 12 (note 3) 2 ns sd/cntl0, ws hold time t hold figure 12 (note 3) 2 ns max9249 gigabit multimedia serial link serializer with lvds system interface
6 ______________________________________________________________________________________ typical operating characteristics (v dvdd = v avdd = v iovdd = 1.8v, v lvdsvdd = 3.3v, t a = +25 n c, unless otherwise noted.) total supply current vs. rxclkin_ frequency (3-channel mode) max9249 toc01 rxclkin frequency (mhz) total supply current (ma) 85 65 45 25 120 130 preemp = 0x01 to 0x04 preemp = 0x00 140 150 160 170 110 5 105 preemp = 0x0b to 0x0f prbs pattern total supply current vs. rxclkin_ frequency (4-channel mode) max9249 toc02 rxclkin frequency (mhz) total supply current (ma) 65 50 35 20 125 130 135 140 145 150 155 160 165 120 58 0 prbs pattern preemp = 0x0b to 0x0f preemp = 0x01 to 0x04 preemp = 0x00 output power spectrum vs. rxclkin_ frequency max9249 toc03 rxclkin frequency (mhz) output power spectrum (dbm) 34.5 33.5 32.5 31.5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 30.5 35.5 f rxclkin_ = 33mhz 0% spread 2% spread 4% spread 0.5% spread maximum pclk frequency vs. stp cable length (ber < 10 -9 ) max9249 toc05 stp cable length (m) maximum pclk frequency (mhz) 15 10 5 20 40 60 80 100 120 0 02 0 optimum pe/eq settings no pe, eqs = low no pe, eqs = low ber can be as low as 10 -12 for cable lengths less than 10m output power spectrum vs. rxclkin_ frequency max9249 toc04 rxclkin frequency (mhz) output power spectrum (dbm) 17.5 17.0 16.5 16.0 15.5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 15.0 18.0 f rxclkin_ = 16.5mhz 0% spread 2% spread 4% spread 0.5% spread maximum rxclkin_ frequency vs. 10m stp cable c l (ber < 10 -9) max9249 toc06 stp cable load capacitance (pf) maximum rxclkin frequency (mhz) 8 6 4 2 20 40 60 80 100 120 0 01 0 no pe, eqs = low no pe, eqs = high optimum pe/eq settings ber can be as low as 10 -12 for c l < 4pf for optimum pe/eq settings max9249 gigabit multimedia serial link serializer with lvds system interface
_______________________________________________________________________________________ 7 pin description pin configuration rxin1+ 4 lvdsvdd 5 agnd 6 rxin2- 7 rxin2+ 8 rxclkin- 9 rxclkin+ 10 rxin3- 11 rxin3+ 12 rxin0- 1 rxin0+ 2 rxin1- 3 33 32 31 30 29 28 27 26 25 36 35 34 iovdd gnd dvdd agnd cntl2 cntl1 ws sck sd/cntl0 avdd lvdsvdd agnd iovdd gnd dvdd n.c. bws pwdn cds ms autos n.c. avdd agnd 37 38 39 40 41 42 43 44 45 46 47 48 ep* *exposed pad. top view 24 23 22 21 20 19 18 17 16 15 14 13 max9249 lmn0 avdd out+ out- agnd lmn1 ssen tx/scl rx/sda drs int lflt + tqfp pin name function 1C4, 7, 8, 11, 12 rxin_-, rxin_+ differential lvds data inputs. set bws = low (3-channel mode) to use rxin0_ to rxin2_. set bws = high (4-channel mode) to use rxin0_ to rxin3_. 5, 14 lvdsvdd 3.3v lvds power supply. bypass lvdsvdd to agnd with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller value capacitor closest to lvdsvdd. 6, 13, 21, 29, 48 agnd analog ground 9, 10 rxclkin-, rxclkin+ lvds input for the lvds clock 15, 32, 47 avdd 1.8v analog power supply. bypass avdd to agnd with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller value capacitor closest to avdd. 16 sd/cntl0 i 2 s serial-data input with internal pulldown to gnd. disable i 2 s to use sd/cntl0 as an additional input. 17 sck i 2 s serial-clock input with internal pulldown to gnd 18 ws i 2 s word-select input with internal pulldown to gnd 19 cntl1 control input 1 with internal pulldown to gnd. data is latched every rxclkin_ cycle (figure 7). cntl1 is not available in 3-channel mode. drive bws high (4-channel mode) to use this input. cntl1 or res (res from vesa standard panel specification) is mapped to din27 (see the reserved bit (res) section). max9249 gigabit multimedia serial link serializer with lvds system interface
8 ______________________________________________________________________________________ pin description (continued) pin name function 20 cntl2 control input 2 with internal pulldown to gnd. data is latched every rxclkin_ cycle (figure 7). cntl2 is not available in 3-channel mode. drive bws high (4-channel mode) to use this input. cntl2 is mapped to din28. 22, 39 dvdd 1.8v digital power supply. bypass dvdd to gnd with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller value capacitor closest to dvdd. 23, 38 gnd digital and i/o ground 24, 37 iovdd i/o supply voltage. 1.8v to 3.3v logic i/o power supply. bypass iovdd to gnd with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smallest value capacitor closest to iovdd. 25 rx/sda receive/serial data. uart receive or i 2 c serial-data input/output with internal 30k i pullup to iovdd. in uart mode, rx/sda is the rx input of the max9249s uart. in i 2 c mode, rx/sda is the sda input/output of the max9249s i 2 c master. 26 tx/scl transmit/serial clock. uart transmit or i 2 c serial-clock output with internal 30k i pullup to iovdd. in uart mode, tx/scl is the tx output of the max9249s uart. in i 2 c mode, tx/scl is the scl output of the max9249s i 2 c master. 27 ssen spread-spectrum enable. serial link spread-spectrum enable input requires external pulldown or pullup resistors. the state of ssen latches upon power-up or when resuming from power-down mode ( pwdn = low). set ssen = high for q 0.5% spread spectrum on the serial link. set ssen = low to use the serial link without spread spectrum. 28 lmn1 line-fault monitor input 1 (see figure 3 for details) 30, 31 out-, out+ differential cml output+/-. differential outputs of the serial link. 33 lmn0 line-fault monitor input 0 (see figure 3 for details) 34 lflt line fault. active-low, open-drain line-fault output with a 60k i internal pullup resistor. lflt = low indicates a line fault. lflt is high impedance when pwdn = low. 35 int interrupt output to indicate remote side requests. int = low upon power-up and when pwdn = low. a transition on the int input of the gmsl deserializer toggles the max9249s int output. 36 drs data-rate select. data-rate range-selection input requires external pulldown or pullup resistors. set drs = high for rxclkin_ frequencies of 8.33mhz to 16.66mhz (3-channel mode) or 6.25mhz to 12.5mhz (4-channel mode). set drs = low for rxclkin_ frequencies of 16.66mhz to 104mhz (3-channel mode) or 12.5mhz to 78mhz (4-channel mode). 40, 46 n.c. internally not connected. connect to gnd or leave unconnected. 41 bws bus-width select. input width selection requires external pulldown or pullup resistors. set bws = low for 3-channel mode. set bws = high for 4-channel mode. 42 pwdn power-down. active-low power-down input requires external pulldown or pullup resistors. 43 cds control direction selection. control link direction selection input requires external pulldown or pullup resistors. set cds = low for f c use on the max9249 side of the serial link. set cds = high for f c use on the gmsl deserializer side of the serial link. 44 ms mode select. control link mode-selection input requires external pulldown or pullup resistors. set ms = low to select base mode. set ms = high to select the bypass mode. max9249 gigabit multimedia serial link serializer with lvds system interface
_______________________________________________________________________________________ 9 pin description (continued) functional diagram pin name function 45 autos autostart setting. active-low power-up mode-selection input requires external pulldown or pullup resistors. set autos = high to power up the device with no link active. set autos = low to have the max9249 power up the serial link with autorange detection (see tables 8 and 9). ep exposed pad. ep internally connected to agnd. must externally connect ep to the agnd plane for proper thermal and electrical performance. spread pll rev ch rx tx/scl rx/sda audio fifo ws, sd/cntl0, sck fifo lmn0 lmn1 out+ out- filter pll clkdiv line-fault det cml tx uart/i 2 c gmsl deserializer ps term 8b/10b encode parity stp cable, z 0 = 100 i (diff) divide by 7 din[6:0] din[13:7] din[20:14] din[26:21] din27 din28 acb 7x pll sp rxin0+/- rxclkin+/- sp rxin1+/- sp rxin2+/- sp rxin3+/- cntl1 cntl2 mux prbs gen lflt max9249 in- in+ max9249 gigabit multimedia serial link serializer with lvds system interface
10 _____________________________________________________________________________________ figure 2. output waveforms at out+ and out- figure 1. serial-output parameters out- v od v os gnd r l /2 r l /2 out+ out- out+ (out+) - (out-) v os(-) v os(+) ((out+) + (out-))/2 v os(-) v od(-) v od(-) v od = 0v dv os = |v os(+) - v os(-) | dv od = |v od(+) - v od(-) | v od (+) out+ out- v os v od(p) v od(d) serial-bit time max9249 gigabit multimedia serial link serializer with lvds system interface
______________________________________________________________________________________ 11 figure 3. line-fault detector circuit figure 4. worst-case pattern input output logic (out+) lflt reference voltage generator connectors *q1% tolerance output logic (out-) max9249 45ki* lmn1 lmn0 45ki* 1.7v to 1.9v 5ki* 50ki* 50ki* 5ki* twisted pair out+ out- rxclkin+ rxclkin- rxin0+ to rxin3+ rxin0- to rxin3- cntl_ max9249 gigabit multimedia serial link serializer with lvds system interface
12 _____________________________________________________________________________________ figure 6. differential output template figure 7. input setup-and-hold times figure 8. lvds receiver input skew margin figure 5. i 2 c timing parameters p t r p s s t hold t f t set tx/ scl rx/ sda 800mv p-p t tsoj1 2 t tsoj1 2 rxin_+/rxin_- rxclkin+ cntl_ rxclkin- t set t hold v ihmin v ilmax min max internal strobe ideal t rskm t rskm ideal serial-bit time max9249 gigabit multimedia serial link serializer with lvds system interface
______________________________________________________________________________________ 13 figure 10. link startup time figure 9. serializer delay n-1 n first bi tl ast bit nn +1 n-1 n+ 2n +3 rxclkin+ rxclkin- out+/out- rxin_+/rxin_- expanded time scale t sd rxclkin- serial link inactive serial link active channel disabled reverse control channel enabled reverse control channel enabled pwdn must be high rxclkin+ t lock 350s max9249 gigabit multimedia serial link serializer with lvds system interface
14 _____________________________________________________________________________________ figure 11. power-up delay figure 12. input i 2 s timing parameters 350s powered down powered up, serial link inactive powered up, serial link active t pu v ih1 reverse control channel disabled reverse control channel enabled reverse control channel disabled reverse control channel enabled pwdn rxclkin+ rxclkin- ws t hold t set t hold t set t hc t sck t lc sck sd/cntl0 max9249 gigabit multimedia serial link serializer with lvds system interface
______________________________________________________________________________________ 15 detailed description the max9249 serializer with lvds system interface utilizes maxims gmsl technology. the max9249 serial - izer pairs with any gmsl deserializer to form a complete digital serial link for joint transmission of high-speed video, audio, and control data. the max9249 allows a maximum serial payload data rate of 2.5gbps for a greater than 15m stp cable. the serializer operates up to a maximum clock of 104mhz for a 3-channel lvds input or 78mhz for a 4-channel lvds input. this serial link supports display panels from qvga (320 x 240) up to wxga (1280 x 800) with 24-bit color. the 3-channel mode handles three lanes of lvds data (21 bits), uart control signals, and three audio signals. the 4-channel mode handles four lanes of lvds data (28 bits), uart control signals, three audio signals, and/ or up to three auxiliary parallel inputs. the three audio inputs form a standard i 2 s interface, supporting sample rates from 8khz to 192khz and audio word lengths of 4 to 32 bits. the embedded control channel forms a full-duplex, differential, 100kbps to 1mbps uart link between the serializer and deserializer. the ecu, or f c, can be located on the max9249 side of the link (typical for video display), on the deserializer side of the link (typ - ical for image sensing), or on both sides. in addition, the control channel enables ecu/ f c control of peripherals in the remote side, such as backlight control, grayscale gamma correction, camera module, and touch screen. base-mode communication with peripherals uses either i 2 c or the gmsl uart format. a bypass mode enables full-duplex communication using custom uart formats. the max9249 serializer driver preemphasis, along with the channel equalizer on the gmsl deserializer, extends the link length and enhances the link reliability. spread spectrum is available on the max9249 to reduce emi on the serial link and the parallel output of the gmsl dese - rializer. the serial output complies with iso 10605 and iec 61000-4-2 esd protection standards. register mapping the f c configures various operating conditions of the max9249 and gmsl deserializer through internal regis - ters. the default device addresses stored in the r0 and r1 registers of both the max9249 and gsml deserial - izer are 0x80 and 0x90, respectively. write to the r0/r1 registers in both devices to change the device address of the max9249 or gmsl deserializer. table 1. power-up default register map (see table 12) register address (hex) power-up default (hex) power-up default settings (msb first) 0x00 0x80 serid =1000000, serializer device address is 1000 000 reserved = 0 0x01 0x90 desid =1001000, deserializer device address is 1001 000 reserved = 0 0x02 0x1f, 0x3f ss = 000 (ssen = low), ss = 001 (ssen = high), spread-spectrum settings depend on ssen pin state at power-up audioen = 1, i 2 s channel enabled prng = 11, automatically detect the pixel clock range srng = 11, automatically detect serial-data rate 0x03 0x00 autofm = 00, calibrate spread-modulation rate only once after locking sdiv = 000000, autocalibrate sawtooth divider max9249 gigabit multimedia serial link serializer with lvds system interface
16 _____________________________________________________________________________________ vesa standard panel bitmapping and bus-width selection the lvds input has two selectable widths, 3-channel and 4-channel. the max9249 accepts the vesa stan - dard panel 3- or 4-channel lvds ( table 2). inputs on the max9249 are mapped internally, according to figures 13 and 14. in 3-channel mode, rxin3_ and cntl1/cntl2 are not available. for both modes, the sd/cntl0, sck, and ws pins are for i 2 s audio. the max9249 accepts clock rates from 8.33mhz to 104mhz for 3-channel mode and 6.25mhz to 78mhz for 4-channel mode. serial link signaling and data format the max9249 high-speed data serial output uses cml signaling with programmable preemphasis and ac-coupling. the gmsl deserializer uses ac-coupling and programmable channel equalization. when using both the preemphasis and equalization, the max9249/ gmsl deserializer can operate up to 3.125gbps over stp cable lengths to 15m or more. the max9249 serializer scrambles and encodes the lvds input data and sends the 8b/10b coded signal through the serial link. the gmsl deserializer recovers table 1. power-up default register map (see table 12) (continued) register address (hex) power-up default (hex) power-up default settings (msb first) 0x04 0x03, 0x13, 0x83 or 0x93 seren = 0 ( autos = high), seren = 1 ( autos = low), serial link enable default depends on autos pin state at power-up clinken = 0, configuration link disabled prbsen = 0, prbs test disabled sleep = 0 or 1, sleep-mode state depends on cds and autos pin state at power-up (see the link startup procedure section) inttype = 00, base mode uses i 2 c revccen = 1, reverse control channel active (receiving) fwdccen = 1, forward control channel active (sending) 0x05 0x70 i2cmethod = 0, i 2 c packets include register address disfpll = 1, filter pll disabled cmllvl = 11, 400mv cml signal level preemp = 0000, preemphasis off 0x06 0x40 reserved = 01000000 0x07 0x22 reserved = 00100010 0x08 0x0a (read only) reserved = 0000 lfneg = 10, no faults detected lfpos = 10, no faults detected 0x0c 0x70 reserved = 01110000 0x0d 0x0f setint = 0, interrupt output set to low reserved = 00 disres = 0, res mapped to din27 skewadj = 1111, no x7pll clock skew adjustment 0x1e 0x03 (read only) id = 00000011, device id is 0x03 0x1f 0x0x (read only) reserved = 0000 revision = xxxx, revision number max9249 gigabit multimedia serial link serializer with lvds system interface
______________________________________________________________________________________ 17 table 2. bus-width selection using bws *res = reserved (see the reserved bit (res) section for details). figure 13. lvds input timing input bits 3-channel mode (bws = low) 4-channel mode (bws = high) vesa standard panel mapping auxiliary signals mapping vesa standard panel mapping auxiliary signals mapping din[0:5] r[0:5] r[0:5] din[6:11] g[0:5] g[0:5] din[12:17] b[0:5] b[0:5] din[18:20] hs, vs, de hs, vs, de din[21:22] not used not used r6, r7 din[23:24] not used not used g6, g7 din[25:26] not used not used b6, b7 din27 not used not used res* cntl1 din28 not used not used cntl2 sd/cntl0 sd/cntl0 sd/cntl0 din1 cycle n-1 cycle n rxin0+/rxin0- rxclkin+ rxclkin- rxin1+/rxin1- rxin2+/rxin2- din0 din6 din5 din4 din3 din2 din1 din0 din8 din7 din13 din12 din11 din10 din9 din8 din7 din15 din14 din20 din19 din18 din17 din16 din15 din14 rxin3+/rxin3- cntl1 din22 din21 din27 cntl2 din28 sd/cntl0* *with i 2 s enabled; otherwise cntl0 sd* din27 din26 din25 din24 din23 din22 din21 max9249 gigabit multimedia serial link serializer with lvds system interface
18 _____________________________________________________________________________________ the embedded serial clock and then samples, decodes, and descrambles before outputting the data. figures 15 and 16 show the serial-data packet format before scrambling and 8b/10b coding. in 3-channel or 4-chan - nel mode, 21 or 28 bits come from the rxin_ _ lvds inputs. control bits can be mapped to din27 and din28 in 4-channel mode. the audio channel bit (acb) con - tains an encoded audio signal derived from the three i 2 s inputs (sd/cntl0, sck, and ws). the forward control - channel (fcc) bit carries the forward control data. the last bit (pcb) is the parity bit of the previous 23 or 31 bits. reserved bit (res) in 4-channel mode, the max9249 serializes all bits of all four lanes including res by default. set disres (d4 of register 0x0d) to 1 to map cntl1 to din27 instead of res. reverse control channel the max9249 uses the reverse control channel to receive i 2 c/uart and interrupt signals from the gmsl deserializer in the opposite direction of the video stream. the reverse control channel and forward video data coexist on the same twisted pair forming a bidirectional link. the reverse control channel operates independently from the forward control channel. the reverse control channel is available 500 f s after power-up. the max9249 temporarily disables the reverse control channel for 350 f s after starting/stopping the forward serial link. data-rate selection the max9249 uses the drs input to set the rxclkin_ frequency. set drs high for an rxclkin_ frequency of 6.25mhz to 12.5mhz (4-channel mode) or 8.33mhz to 16.66mhz (3-channel mode). set drs low for normal operation with an rxclkin_ frequency of 12.5mhz to 78mhz (4-channel mode) or 16.66mhz to 104mhz (3-channel mode). figure 14. vesa standard panel clock and bit assignment figure 15. 3-channel mode serial link data format r1 cycle n-1 cycle n rxin0+/rxin0- rxclkin+ rxclkin- rxin1+/rxin1- rxin2+/rxin2- r0 g0 r5 r4 r3 r2 r1 r0 g2 g1 b1 b0 g5 g4 g3 g2 g1 b3 b2 de vs hs b5 b4 b3 b2 rxin3+/rxin3- r7 r6 res b7 b6 g7 g6 r7 r6 note: locations of the rgb data and control signals are set according to vesa standard panel bitmap. din0 lvds data (3 channels) din1 din17 din18 din19 din20 acb fcc pcb 24 bits audio channel bit forward control- channel bit packet parity check bit r0 r1 b5 hs vs de max9249 gigabit multimedia serial link serializer with lvds system interface
______________________________________________________________________________________ 19 figure 16. 4-channel mode serial link data format audio channel the i 2 s audio channel supports audio sampling rates from 8khz to 192khz and audio word lengths from 4 bits to 32 bits. the audio bit clock (sck) does not have to be synchronized with rxclkin_. the max9249 auto - matically encodes audio data into a single bit stream synchronous with rxclkin_. the gmsl deserializer decodes the audio stream and stores audio words in a fifo. audio rate detection uses an internal oscillator to continuously determine the audio data rate and output the audio in i 2 s format. the audio channel is enabled by default. when the audio channel is disabled, the audio data on the max9249 and gmsl deserializer is treated as a control pin (cntl0). low rxclkin_ frequencies limit the maximum audio sampling rate. table 3 lists the maximum audio sam - pling rate for various rxclkin_ frequencies. spread- spectrum settings do not affect the i 2 s data rate or ws clock frequency. control channel and register programming the control channel is available for the f c to send and receive control data over the serial link simultane - ously with the high-speed data. configuring the cds pin allows the f c to control the link from either the max9249 or the gmsl deserializer side to support video-display or image-sensing applications. the control channel between the f c and max9249 or gmsl deserializer runs in base mode or bypass mode according to the mode selection (ms) input of the device connected to the f c. base mode is a half-duplex control channel and the bypass mode is a full-duplex control channel. in base mode, the f c is the host and can access the registers of both the max9249 and gmsl deserializer from either side of the link by using the gmsl table 3. maximum audio ws frequency (khz) for various rxclkin_ frequencies din21 lvds data (rxin3_) din22 din25 din26 din27 din28 acb fcc pcb 32 bits audio channel/cntl0 bit forward control- channel bit packet parity check bit r6 r7 b6 din24 g7 din23 g6 b7 cntl2 res/cntl1 din1 lvds data (rxin[2:0]_) din18 din19 din20 r1 din0 r0 hs din17 b5 vs de *din27 from lvds data (rxin3_) or external pin (cntl1). note: locations of the lvds rgb data and control signals are set according to the vesa standard panel bitmap. word length (bits) rxclkin_ frequency (drs = low) (mhz) rxclkin_ frequency (drs = high) (mhz) 12.5 15 16.6 > 20 6.25 7.5 8.33 > 10 8 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 16 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 18 185.5 > 192 > 192 > 192 185.5 > 192 > 192 > 192 20 174.6 > 192 > 192 > 192 174.6 > 192 > 192 > 192 24 152.2 182.7 > 192 > 192 152.2 182.7 > 192 > 192 32 123.7 148.4 164.3 > 192 123.7 148.4 164.3 > 192 max9249 gigabit multimedia serial link serializer with lvds system interface
20 _____________________________________________________________________________________ uart protocol. the f c can also program the peripher - als on the remote side by sending the uart packets to the max9249 or gmsl deserializer, with the uart packets converted to i 2 c by the device on the remote side of the link (gmsl deserializer for lcd or max9249 for image-sensing applications). the f c communicates with a uart peripheral in base mode (through inttype register settings), using the half-duplex default gmsl uart protocol of the max9249/gmsl deserializer. the device addresses of the max9249 and gmsl deserial - izer in base mode are programmable. the default values are 0x80 for the max9249 and 0x90 for the gmsl dese - rializer. in base mode, when the peripheral interface uses i 2 c (default), the max9249/gmsl deserializer convert packets to i 2 c that have device addresses different from those of the max9249 or gmsl deserializer. the converted i 2 c bit rate is the same as the original uart bit rate. in bypass mode, the max9249/gmsl deserializer ignore uart commands from the f c and the f c communi - cates with the peripherals directly using its own defined uart protocol. the f c cannot access the max9249/ gmsl deserializers registers in this mode. peripherals accessed through the forward control channel using the uart interface need to handle at least one rxclkin_ period of jitter due to the asynchronous sampling of the uart signal by rxclkin_. the max9249 embeds control signals going to the gmsl deserializer in the high-speed forward link. do not send a logic-low value longer than 100 f s in either base or bypass mode. the gmsl deserializer uses a proprietary differential line coding to send signals back towards the max9249. the speed of the control channel ranges from 100kbps to 1mbps in both directions. the max9249/ gmsl deserializer automatically detect the control chan - nel bit rate in base mode. packet bit rates can vary up to 3.5x from the previous bit rate (see the changing the clock frequency section). figure 17 shows the uart protocol for writing and reading in base mode between the f c and the max9249/gmsl deserializer. figure 18 shows the uart data format. even parity is used. figures 19 and 20 detail the formats of the sync byte (0x79) and the ack byte (0xc3). the f c and the connected slave chip generate the sync byte and ack byte, respectively. events such as device wake-up and interrupt generate transitions on the control channel that should be ignored by the f c. data written to the max9249/gmsl deserializer registers does not take effect until after the acknowledge byte is sent. this allows the f c to verify write commands received without error, even if the result of the write command directly affects the serial link. the slave uses the sync byte to synchronize with the host uart data rate automatically. if the int or ms inputs of the gmsl deserializer toggles while there is control-channel communication, the con - trol-channel communication may be corrupted. in the event of a missed acknowledge, the f c should assume there was an error in the packet when the slave device receives it, or that an error occurred during the response from the slave device. in base mode, the f c must keep the uart tx/rx lines high for 16 bit times before starting to send a new packet. as shown in figure 21, the remote-side device converts the packets going to or coming from the peripherals from the uart format to the i 2 c format and vice versa. the remote device removes the byte number count and adds or receives the ack between the data bytes of i 2 c. the i 2 cs data rate is the same as the uart data rate. interfacing command-byte-only i 2 c devices the max9249 and gmsl deserializer uart-to-i 2 c con - version interfaces with devices that do not require regis - ter addresses, such as the max7324 gpio expander. in this mode, the i 2 c master ignores the register address byte and directly reads/writes the subsequent data bytes (figure 22). change the communication method of the i 2 c master using the i2cmethod bit. i2cmethod = 1 sets command-byte-only mode, while i2cmethod = 0 sets normal mode where the first byte in the data stream is the register address. interrupt control the int pin of the max9249 is the interrupt output and the int pin of the gmsl deserializer is the interrupt input. the interrupt output on the max9249 follows the transitions at the interrupt input. this interrupt function supports remote-side functions such as touch-screen peripherals, remote power-up, or remote monitoring. interrupts that occur during periods where the reverse control channel is disabled, such as link startup/shut - down, are automatically resent once the reverse control channel becomes available again. bit d4 of register 0x06 in the gmsl deserializer also stores the interrupt input state. the int output of the max9249 is low after power-up. in addition, the f c can set the int output of max9249 by writing to the setint register bit. in normal operation, the state of the interrupt output changes when the interrupt input on the gmsl deserializer toggles. max9249 gigabit multimedia serial link serializer with lvds system interface
______________________________________________________________________________________ 21 figure 17. gmsl uart protocol for base mode figure 18. gmsl uart data format for base mode figure 19. sync byte (0x79) figure 20. ack byte (0xc3) write data format sync dev addr + r/w reg addr number of bytes sync dev addr + r/w reg addr number of bytes byte 1 byte n ack byte n byte 1 ack master reads from slave read data frmat master writes to slave master writes to slave master reads from slave start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 1 uart frame frame 1 frame 2 frame 3 stop start stop start start d0 10011110 d1 d2 d3 d4 d5 d6 d7 parity stop start d0 11000011 d1 d2 d3 d4 d5 d6 d7 parity stop max9249 gigabit multimedia serial link serializer with lvds system interface
22 _____________________________________________________________________________________ figure 21. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 0) figure 22. format conversion between uart and i 2 c in command-byte-only mode (i2cmethod = 1) 11 sync frame register address number of bytes device id + wr data 0 dev id a 11 11 11 11 data n 11 11 s 1 1 1 ack frame 7 : master to slave 8 max9249/gmsl deserializer peripheral w 1 reg addr 8 a 11 81 11 sync frame register address number of bytes device id + rd 11 11 11 11 ack frame data 0 11 data n 11 uart-to-i 2 c conversion of write packet (i2cmethod = 0) uart-to-i 2 c conversion of read packet (i2cmethod = 0) s: start p: stop a: acknowledge : slave to master data 0a data na p dev id a s 11 7 w 1 dev id a s 11 7 r 1 data np 1 8 a 1 data 0 8 a 1 reg addr 8 a 1 fc max9249/gmsl deserializer fc max9249/gmsl deserializer max9249/gmsl deserializer peripheral : master to slave max9249/gmsl deserializer max9249/gmsl deserializer max9249/gmsl deserializer uart-to-i 2 c conversion of read packet (i2cmethod = 1) uart-to-i 2 c conversion of write packet (i2cmethod = 1) fc max9249/gmsl deserializer fc sync frame 11 11 11 11 11 11 11 11 11 11 11 11 11 11 device id + rd register address number of bytes sync frame device id + wr register address number of bytes data 0 data n ack frame ack frame data 0 data n data n a data 0 wa dev id s ap peripheral peripheral s 11 18 88 1 1 1 17 11 8 11 1 7 dev id ra aa p data 0 data n : slave to master s: start p: stop a: acknowledge max9249 gigabit multimedia serial link serializer with lvds system interface
______________________________________________________________________________________ 23 *negative preemphasis levels denote deemphasis. preemphasis driver the serial line driver in the max9249 employs cur - rent-mode logic (cml) signaling. the driver can be programmed to generate a preemphasized waveform according to the cable length and characteristics. there are 13 preemphasis settings, as shown in table 4. negative preemphasis levels are deemphasis levels in which the swing is the same as normal, but the no-tran - sition data is deemphasized. program the preemphasis levels through register 0x05 d[3:0] of the max9249. this preemphasis function compensates the high-frequency loss of the cable and enables reliable transmission over longer link distances. additionally, a lower power-drive mode can be entered by programming cmllvl bits (0x05 d[5:4]) to reduce the driver strength down to 75% (cmllvl = 10) or 50% (cmllvl = 01) from 100% (cmllvl = 11, default). spread spectrum to reduce the emi generated by the transitions on the serial link and outputs of the gmsl deserializer, both the max9249 and gmsl deserializer support spread spectrum. turning on spread spectrum on the max9249 spreads the serial data and the gmsl deserializer out - puts. do not enable spread for both the max9249 and gmsl deserializer. the six selectable spread-spectrum rates at the max9249 serial output are 0.5%, 1%, 1.5%, 2%, 3%, and 4% (table 5). some spread- spectrum rates can only be used at lower rxclkin_ frequencies (table 6). there is no rxclkin_ frequency limit for the 0.5% spread rate. set the max9249 ssen input high to select 0.5% spread at power-up and ssen input low to select no spread at power-up. the state of ssen is latched upon power-up or when resuming from power-down mode. whenever the max9249 spread spectrum is turned on or off, the serial link automatically restarts and remains unavailable while the gmsl deserializer relocks to the serial data. turning on spread spectrum on the max9249 or gmsl deserializer does not affect the audio data stream. changes in the max9249 spread settings only affect the gmsl deserializer mclk output if it is derived from rxclkin_ (mclksrc = 0). table 4. cml driver strength (default level, cmllvl = 11) table 5. serial output spread preemphasis level (db)* preemphasis setting (0x05, d[3:0]) i cml (ma) i pre (ma) single-ended voltage swing max (mv) min (mv) -6.0 0100 12 4 400 200 -4.1 0011 13 3 400 250 -2.5 0010 14 2 400 300 -1.2 0001 15 1 400 350 0 0000 16 0 400 400 1.1 1000 16 1 425 375 2.2 1001 16 2 450 350 3.3 1010 16 3 475 325 4.4 1011 16 4 500 300 6.0 1100 15 5 500 250 8.0 1101 14 6 500 200 10.5 1110 13 7 500 150 14.0 1111 12 8 500 100 ss spread (%) 000 no spread spectrum. power-up default when ssen = low. 001 q 0.5% spread spectrum. power-up default when ssen = high. 010 q 1.5% spread spectrum 011 q 2% spread spectrum 100 no spread spectrum 101 q 1% spread spectrum 110 q 3% spread spectrum 111 q 4% spread spectrum max9249 gigabit multimedia serial link serializer with lvds system interface
24 _____________________________________________________________________________________ both devices include a sawtooth divider to control the spread-modulation rate. autodetection or manual pro - gramming of the rxclkin_ operation range guarantees a spread-spectrum modulation frequency within 20khz to 40khz. additionally, manual configuration of the sawtooth divider (sdiv, 0x03 d[5:0]) allows the user to set a modulation frequency according to the rxclkin_ frequency. always keep the modulation frequency between 20khz to 40khz to ensure proper operation. manual programming of the spread-spectrum divider the modulation rate for the max9249 relates to the rxclkin_ frequency as follows: ( ) rxclkin_ m f f 1 drs mod sdiv = + where: f m = modulation frequency drs = drs pin input value (0 or 1) f rxclkin_ = lvds clock frequency mod = modulation coefficient given in table 7 sdiv = 6-bit sdiv setting, manually programmed by the f c to program the sdiv setting, first look up the modulation coefficient according to the part number and desired bus-width and spread-spectrum settings. solve the above equation for sdiv using the desired pixel clock and modu - lation frequencies. if the calculated sdiv value is larger than the maximum allowed sdiv value in table 7, set sdiv to the maximum value. sleep mode the max9249/gmsl deserializer include low-power sleep mode to reduce power consumption on the device not attached to the f c (the gmsl deserializer in lcd applications and the max9249 in camera applications). set the corresponding remote ics sleep bit to 1 to initi - ate sleep mode. the max9249 sleeps immediately after table 6. spread-spectrum rate limitations table 7. modulation coefficients and maximum sdiv settings 3-channel mode rxclkin_ frequency (mhz) 4-channel mode rxclkin_ frequency (mhz) serial link bit rate (mbps) available spread rates < 33.3 < 25 < 1000 all rates available 33.3 to < 66.7 20 to < 50 1000 to < 2000 1.5%, 1.0%, 0.5% 66.7 50 2000 0.5% bus-width mode spread-spectrum setting (%) modulation coefficient (decimal) sdiv upper limit (decimal) 4-channel 0.5 104 63 1 104 40 1.5 152 54 2 204 30 3 152 27 4 204 15 3-channel 0.5 80 63 1 80 52 1.5 112 63 2 152 42 3 112 37 4 152 21 max9249 gigabit multimedia serial link serializer with lvds system interface
______________________________________________________________________________________ 25 table 8. startup selection for video-display applications (cds = low) setting its sleep = 1. the gmsl deserializer sleeps after serial link inactivity or 8ms (whichever arrives first) after setting its sleep = 1. see the link startup procedure section for details on waking up the device for different f c and starting conditions. the f c side device cannot enter into sleep mode. if an attempt is made to program the f c side device for sleep, the sleep bit remains 0. use the pwdn input pin to bring the f c side device into a low-power state. configuration link mode the max9249 includes a low-speed configuration link to allow control-data connection between the two devices in the absence of a valid clock input. in either display or camera applications, the configuration link can be used to program equalizer/preemphasis or other registers before establishing the video link. an internal oscillator provides rxclkin_ for establishing the serial configura - tion link between the max9249 and gmsl deserializer. set clinken = 1 on the max9249 to turn on the con - figuration link. the configuration link remains active as long as the video link has not been enabled. the video link overrides the configuration link and attempts to lock when seren = 1. link startup procedure table 8 lists four startup cases for video-display applica - tions. table 9 lists two startup cases for image-sensing applications. in either video-display or image-sensing applications, the control link is always available after the high-speed data link or the configuration link is estab - lished and the max9249/gmsl deserializer registers or the peripherals are ready for programming. video-display applications for the video-display application, with a remote display unit, connect the f c to the serializer (max9249) and set cds = low for both the max9249 and gmsl deserializer. table 8 summarizes the four startup cases based on the settings of autos and ms. case 1: autostart mode after power-up or when pwdn transitions from low to high for both the serializer and deserializer, the serial link establishes if a stable rxclkin_ is present. the max9249 locks to rxclkin_ and sends the serial data to the gmsl deserializer. the gmsl deserializer then detects activity on the serial link and locks to the input serial data. case autos (max9249) max9249 power-up state ms (gmsl deserializer) gmsl deserializer power-up state link startup mode 1 low serialization enabled low normal (sleep = 0) both devices power up with serial link active (autostart) 2 high serialization disabled high sleep mode (sleep = 1) serial link is disabled and the gmsl deserializer powers up in sleep mode. set seren = 1 or clinken = 1 in the max9249 to start the serial link and wake up the gmsl deserializer. 3 high serialization disabled low normal (sleep = 0) both devices power up in normal mode with the serial link disabled. set seren = 1 or clinken = 1 in the max9249 to start the serial link. 4 low serialization enabled high sleep mode (sleep = 1) gmsl deserializer starts in sleep mode. link autostarts upon max9249 power-up. use this case when the gmsl deserializer powers up before the max9249. max9249 gigabit multimedia serial link serializer with lvds system interface
26 _____________________________________________________________________________________ case 2: standby start mode after power-up or when pwdn transitions from low to high for both the serializer and deserializer, the gmsl deserializer starts up in sleep mode, and the max9249 stays in standby mode (does not send serial data). use the f c and program the max9249 to set seren = 1 to establish a video link or clinken = 1 to establish the configuration link. after locking to a stable rxclkin_ (for seren = 1) or the internal oscillator (for clinken = 1), the max9249 sends a wake-up signal to the deserializer. the gmsl deserializer exits sleep mode after locking to the serial data and sets sleep = 0. if after 8ms the dese - rializer does not lock to the input serial data, the gmsl deserializer goes back to sleep, and the internal sleep bit remains set (sleep = 1). case 3: remote side autostart mode after power-up or when pwdn transitions from low to high, the remote device (gmsl deserializer) starts up and tries to lock to an incoming serial signal with sufficient power. the host side (max9249) is in standby mode and does not try to establish a link. use the f c and program the max9249 to set seren = 1 (and apply a stable rxclkin_) to establish a video link or clinken = 1 to establish the configuration link. in this case, the gmsl deserializer ignores the short wake-up signal sent from max9249. figure 23. state diagram, cds = low (lcd application) table 9. startup selection for image-sensing applications (cds = high) power-down or power-off power-on idle config link operating all states video link locking video link unlocked autos pin setting low high 1 0 seren bit power-up value pwdn = low or power-off seren = 1, rxclkin_ running seren = 0, or no rxclkin_ seren = 0, no rxclkin_ pwdn = high power-on, autos = low config link starting program registers video link operating prbsen = 0 prbsen = 1 video link prbs test clinken = 0 or seren = 1 clinken = 1 clinken = 0 or seren = 1 config link unlocked video link locked locked config link pwdn = high, power-on autos = low case autos (max9249) max9249 power-up state gmsl deserializer power-up state link startup mode 1 low serialization enabled normal (sleep = 0) autostart 2 high sleep mode (sleep = 1) normal (sleep = 0) max9249 is in sleep mode. wake up the max9249 through the control channel ( f c attached to the gmsl deserializer). max9249 gigabit multimedia serial link serializer with lvds system interface
______________________________________________________________________________________ 27 figure 24. state diagram, cds = high (camera application) case 4: remote side in sleep mode after power-up or when pwdn transitions from low to high, the remote device (gmsl deserializer) starts up in sleep mode. the high-speed link establishes automati - cally after max9249 powers up with a stable rxclkin_ and sends a wake-up signal to the gmsl deserializer. use this mode in applications where the gmsl deserial - izer powers up before the max9249. image-sensing applications for image-sensing applications, connect the f c to the gmsl deserializer and set cds = high for both the max9249 and gmsl deserializer. the gmsl deserial - izer powers up normally (sleep = 0) and continuously tries to lock to a valid serial input. table 9 summarizes both startup cases, based on the state of the max9249 autos pin. case 1: autostart mode after power-up, or when pwdn transitions from low to high, the max9249 locks to a stable rxclkin_ and sends the high-speed data to the gmsl deserializer. the gmsl deserializer locks to the serial data and outputs the video data and clock. case 2: sleep mode after power-up or when pwdn transitions from low to high, the max9249 starts up in sleep mode. to wake up the max9249, use the f c to send a gmsl protocol uart frame containing at least three rising edges (e.g., 0x66), at a bit rate no greater than 1mbps. the low-power wake- up receiver of the max9249 detects the wake-up frame over the reverse control channel and powers up. reset the sleep bit (sleep = 0) of the max9249 using a regular control channel write packet to power up the device fully. send the sleep bit write packet at least 500 f s after the wake-up frame. the max9249 goes back to sleep mode if its sleep bit is not cleared within 5ms (min) after detect - ing a wake-up frame. applications information self-prbs test the max9249/gmsl deserializer link includes a prbs pattern generator and bit-error verification function. set prbsen =1 (0x04 d5) first in the max9249 and then the gmsl deserializer to start the prbs test. set prbsen =0 (0x04 d5) first in the gmsl deserializer and then the max9249 to exit the prbs self-test. the gmsl deserial - izer uses an 8-bit register (0x0e) to count the number of detected errors. the control link also controls the start and stop of the error counting. during prbs mode, the device does not count decoding errors and the gmsl deserializer err output reflects prbs errors only. refer to the respective gmsl deserializer data sheet for more details. low high 1 0 0 seren sleep 1 power-up value seren = 0 for > 8ms video link operating video link prbs test wake-up sleep = 1 wake-up signal reverse link config link started clinken = 0 or seren = 1 clinken = 1 unlocked locked config link config link sleep = 0, sleep power-on idle power-off all states pwdn = low or sleep = 1 power-down or power-off autos = low pwdn = high, power-on video link locking autos pin setting config link operating program registers clinken = 0 or seren = 1 video link locked video link unlocked prbsen = 0 prbsen = 1 seren = 1, rxclkin_ running seren = 0 or no rxclkin_ seren = 0 or no rxclkin_ pwdn = high, power-on, autos = high sleep = 0, sleep = 1 max9249 gigabit multimedia serial link serializer with lvds system interface
28 _____________________________________________________________________________________ microcontrollers on both sides of the gmsl link (dual c control) usually the microcontroller is either on the serializer (max9249) side for video-display applications or on the deserializer side for image-sensing applications. for the former case, both the cds pins of the max9249/gmsl deserializer are set to low, and for the latter case, the cds pins are set to high. however, if the cds pin of the max9249 is low and the same pin of the gmsl dese - rializer is high, then the max9249/gmsl deserializer connect to both f cs simultaneously. in such a case, the f cs on either side can communicate with the max9249/ gmsl deserializer. contentions of the control link can happen if the f cs on both sides are using the link at the same time. the max9249/gmsl deserializer do not provide the solution for contention avoidance. the serializer/deserializer do not send an acknowledge frame when communication fails due to contention. users can always implement a higher layer protocol to avoid the contention. in addi - tion, if uart communication across the serial link is not required, the f cs can disable the forward and reverse control channel through the revccen and fwdccen bits (0x04 d[1:0]) in the max9249/gmsl deserializer. uart communication across the serial link is stopped and contention between f cs no longer occurs. during dual f cs operation, if one of the cds pins on either side changes state, the link resumes the corresponding state described in the link startup procedure section. as an example of dual f c use in an image-sensing appli - cation, the max9249 can be in sleep mode and waiting for wake-up by the gmsl deserializer. after wake-up, the serializer-side f c sets the max9249 cds pin low and assumes master control of the max9249 registers. jitter-filtering pll in some applications, the input clock to the max9249 (rxclkin_) includes jitter that reduces link reliability. the max9249 has a programmable narrow-band jitter- filtering pll to attenuate frequency components outside the plls bandwidth (< 100khz, typ). enable the jitter- filtering pll by setting disfpll = 0 (0x05 d6). changing the clock frequency both the video clock rate (f rxclkin_ ) and the control- channel clock rate (f uart ) can be changed on-the-fly to support applications with multiple clock speeds. it is recommended to enable the serial link after rxclkin_ stabilizes. stop rxclkin_ for 5 f s and restart the serial link or toggle seren after each change in the rxclkin_ frequency to recalibrate any automatic settings if a clean frequency change cannot be guaranteed. the reverse control channel remains unavailable for 350 f s after serial link start or stop. limit on-the-fly changes in f uart to fac - tors of less than 3.5 at a time to ensure that the device recognizes the uart sync pattern. for example, when lowering the uart frequency from 1mbps to 100kbps, first send data at 333kbps and then at 100kbps to have reduction ratios of 3 and 3.333, respectively. lock output loopback for quick loss-of-lock notification, the gmsl deserializer can loop back its lock output to the max9249 using the int signal. connect the lock output to the int input of the gmsl deserializer. the interrupt output on the max9249 follows the transitions at the lock output of the gmsl deserializer. reverse control-channel com - munication does not require an active forward link to operate and accurately tracks the lock status of the video link. lock asserts for video link only and not for the configuration link. line-fault detection the line-fault detector in the max9249 monitors for line failures such as short to ground, short to power supply, and open link for system fault diagnosis. figure 3 shows the required external resistor connections. lflt = low when a line fault is detected and lflt = high when the line returns to normal. the line-fault type is stored in 0x08 d[3:0] of the max9249. the fault-detector thresh - old voltages are referenced to the max9249 ground. additional passive components set the dc level of the cable (figure 3). if the max9249 and gmsl deserializer grounds are different, the link dc voltage during normal operation can vary and cross one of the fault-detection thresholds. for the fault-detection circuit, select the resistors power rating to handle a short to the battery and use surface-mount resistors with small case size to minimize parasitic effects to the high-speed signal. table 10 lists the mapping for line-fault types. max9249 gigabit multimedia serial link serializer with lvds system interface
______________________________________________________________________________________ 29 table 10. line-fault mapping choosing i 2 c/uart pullup resistors both i 2 c/uart open-drain lines require pullup resis - tors to provide a logic-high level. there are trade-offs between power dissipation and speed, and a compro - mise made in choosing pullup resistor values. every device connected to the bus introduces some capaci - tance even when the device is not in operation. i 2 c specifies 300ns rise times to go from low to high (30% to 70%) for fast mode, which is defined for data rates up to 400kbps (see the i 2 c specifications in the ac electrical characteristics section for details). to meet the fast- mode rise-time requirement, choose the pullup resistors so that rise time t r = 0.85 x r pullup x c bus < 300ns. the waveforms are not recognized if the transition time becomes too slow. the max9249 supports i 2 c/uart rates up to 1mbps. ac-coupling ac-coupling isolates the receiver from dc voltages up to the voltage rating of the capacitor. four capacitors two at the serializer output and two at the deserializer inputare needed for proper link operation and to pro - vide protection if either end of the cable is shorted to a high voltage. ac-coupling blocks low-frequency ground shifts and low-frequency common-mode noise. selection of ac-coupling capacitors voltage droop and the digital sum variation (dsv) of transmitted symbols cause signal transitions to start from different voltage levels. because the transition time is finite, starting the signal transition from different volt - age levels causes timing jitter. the time constant for an ac-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. the rc network for an ac-coupled link consists of the cml receiver termination resistor (r tr ), the cml driver termination resistor (r td ), and the series ac-coupling capacitors (c). the rc time constant for four equal-value series capacitors is (c x (r td + r tr ))/4. r td and r tr are required to match the transmission line impedance (usually 100 i ). this leaves the capacitor selection to change the system time con - stant. use at least 0.2 f f high-frequency surface-mount ceramic capacitors, with sufficient voltage rating to with - stand a short to battery, to pass the lower speed reverse control-channel signal. use capacitors with a case size less than 3.2mm x 1.6mm to have lower parasitic effects to the high-speed signal. power-supply circuits and bypassing the max9249 uses a v avdd and v dvdd of 1.7v to 1.9v, and a v lvdsvdd of 3.0v to 3.6v. all single-ended inputs and outputs on the max9249 derive power from a v iovdd of 1.7v to 3.6v, which scale with iovdd. proper voltage-supply bypassing is essential for high-frequency circuit stability. cables and connectors interconnect for cml typically has a differential imped - ance of 100 i . use cables and connectors that have matched differential impedance to minimize impedance discontinuities. twisted-pair and shielded twisted-pair cables tend to generate less emi due to magnetic-field canceling effects. balanced cables pick up noise as common mode rejected by the cml receiver. table 11 lists the suggested cables and connectors used in the gmsl link. register address bits name value line-fault type 0x08 d[3:2] lfneg 00 negative cable wire shorted to battery 01 negative cable wire shorted to ground 10 normal operation 11 negative cable wire open d[1:0] lfpos 00 positive cable wire shorted to battery 01 positive cable wire shorted to ground 10 normal operation 11 positive cable wire open max9249 gigabit multimedia serial link serializer with lvds system interface
30 _____________________________________________________________________________________ table 11. suggested connectors and cables for gmsl board layout separate the digital signals and cml/lvds high-speed signals to prevent crosstalk. use a four-layer pcb with separate layers for power, ground, cml/lvds, and digital signals. layout pcb traces close to each other for a 100 i differential characteristic impedance. the trace dimensions depend on the type of trace used (microstrip or stripline). note that two 50 i pcb traces do not have 100 i differential impedance when brought close togetherthe impedance goes down when the traces are brought closer. route the pcb traces for a cml/lvds channel (there are two conductors per cml/lvds channel) in parallel to maintain the differential characteristic impedance. avoid vias. keep pcb traces that make up a differential pair equal length to avoid skew within the differential pair. esd protection the max9249 esd tolerance is rated for human body model, iec 61000-4-2, and iso 10605. the iso 10605 and iec 61000-4-2 standards specify esd tolerance for electronic systems. cml/lvds i/o are tested for iso 10605 esd protection and iec 61000-4-2 esd protec - tion. all pins are tested for the human body model. the human body model discharge components are c s = 100pf and r d = 1.5k i (figure 25). the iec 61000-4-2 discharge components are c s = 150pf and r d = 330 i (figure 26). the iso 10605 discharge components are c s = 330pf and r d = 2k i (figure 27). figure 25. human body model esd test circuit figure 26. iec 61000-4-2 contact discharge esd test circuit figure 27. iso 10605 contact discharge esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 1mi r d 1.5ki c s 100pf c s 150pf storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 330i storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 2ki c s 330pf vendor connector cable jae electronics, inc. mx38-ff a-bw-lxxxxx nissei electric co., ltd. gt11l-2s f-2wme awg28 rosenberger hochfrequenztechnik gmbh d4s10a-40ml5-z dacar 538 max9249 gigabit multimedia serial link serializer with lvds system interface
______________________________________________________________________________________ 31 table 12. register table (see table 1 for default value details) register address bits name value function default value 0x00 d[7:1] serid xxxxxxx serializer device address 1000000 d0 0 reserved 0 0x01 d[7:1] desid xxxxxxx deserializer device address 1001000 d0 0 reserved 0 0x02 d[7:5] ss 000 no spread spectrum. power-up default when ssen = low. 000, 001 001 q 0.5% spread spectrum. power-up default when ssen = high. 010 q 1.5% spread spectrum 011 q 2% spread spectrum 100 no spread spectrum 101 q 1% spread spectrum 110 q 3% spread spectrum 111 q 4% spread spectrum d4 audioen 0 disable i 2 s channel 1 1 enable i 2 s channel d[3:2] prng 00 12.5mhz to 25mhz pixel clock 11 01 25mhz to 50mhz pixel clock 10 50mhz to 104mhz pixel clock 11 automatically detect the pixel clock range d[1:0] srng 00 0.5 to 1gbps serial-bit rate 11 01 1 to 2gps serial-bit rate 10 2 to 3.125gbps serial-bit rate 11 automatically detect serial-bit rate 0x03 d[7:6] autofm 00 calibrate spread-modulation rate only once after locking 00 01 calibrate spread-modulation rate every 2ms after locking 10 calibrate spread-modulation rate every 16ms after locking 11 calibrate spread-modulation rate every 256ms after locking d[5:0] sdiv 000000 autocalibrate sawtooth divider 000000 xxxxxx manual sdiv setting. see the manual programming of the spread-spectrum divider section . max9249 gigabit multimedia serial link serializer with lvds system interface
32 _____________________________________________________________________________________ table 12. register table (see table 1 for default value details) (continued) register address bits name value function default value 0x04 d7 seren 0 disable serial link. power-up default when autos = high. reverse control-channel com - munication remains unavailable for 350 f s after the max9249 starts/stops the serial link. 0, 1 1 enable serial link. power-up default when autos = low. reverse control-channel commu - nication remains unavailable for 350 f s after the max9249 starts/stops the serial link. d6 clinken 0 disable configuration link 0 1 enable configuration link d5 prbsen 0 disable prbs test 0 1 enable prbs test d4 sleep 0 normal mode. default value depends on cds and autos pin values at power-up. 0, 1 1 activate sleep mode. default value depends on cds and autos pin values at power-up. d[3:2] inttype 00 base mode uses i 2 c peripheral interface 00 01 base mode uses uart peripheral interface 10, 11 base mode peripheral interface disabled d1 revccen 0 disable reverse control channel from deserializer (receiving) 1 1 enable reverse control channel from deserializer (receiving) d0 fwdccen 0 disable forward control channel to deserializer (sending) 1 1 enable forward control channel to deserializer (sending) max9249 gigabit multimedia serial link serializer with lvds system interface
______________________________________________________________________________________ 33 table 12. register table (see table 1 for default value details) (continued) register address bits name value function default value 0x05 d7 i2cmethod 0 i 2 c conversion sends the register address 0 1 disable sending of i 2 c register address (command-byte-only mode) d6 disfpll 0 filter pll active 1 1 filter pll disabled d[5:4] cmllvl 00 do not use 11 01 200mv cml signal level 10 300mv cml signal level 11 400mv cml signal level d[3:0] preemp 0000 preemphasis off 0000 0001 -1.2db preemphasis 0010 -2.5db preemphasis 0011 -4.1db preemphasis 0100 -6.0db preemphasis 0101 do not use 0110 do not use 0111 do not use 1000 1.1db preemphasis 1001 2.2db preemphasis 1010 3.3db preemphasis 1011 4.4db preemphasis 1100 6.0db preemphasis 1101 8.0db preemphasis 1110 10.5db preemphasis 1111 14.0db preemphasis 0x06 d[7:0] 01000000 reserved 01000000 0x07 d[7:0] 00100010 reserved 00100010 0x08 d[7:4] 0000 reserved 0000 (read only) d[3:2] lfneg 00 negative cable wire shorted to battery 10 (read only) 01 negative cable wire shorted to ground 10 normal operation 11 negative cable wire open d[1:0] lfpos 00 positive cable wire shorted to battery 10 (read only) 01 positive cable wire shorted to ground 10 normal operation 11 positive cable wire open 0x0c d[7:0] 01110000 reserved 01110000 max9249 gigabit multimedia serial link serializer with lvds system interface
34 _____________________________________________________________________________________ table 12. register table (see table 1 for default value details) (continued) x = dont care. register address bits name value function default value 0x0d d7 setint 0 set int low when setint transitions from 1 to 0 0 1 set int high when setint transitions from 0 to 1 d[6:5] 00 reserved 00 d4 disres 0 res (lvds interface) mapped to din27 0 1 cntl1 mapped to din27 d[3:0] skewadj 0000 adjust x7 pll clock skew + 50ps 1111 0001 adjust x7 pll clock skew + 100ps 0010 adjust x7 pll clock skew + 200ps 0011 adjust x7 pll clock skew + 250ps 0100 adjust x7 pll clock skew + 300ps 0101 adjust x7 pll clock skew + 350ps 0110 adjust x7 pll clock skew + 400ps 0111 do not use 1000 adjust x7 pll clock skew - 50ps 1001 adjust x7 pll clock skew - 100ps 1010 adjust x7 pll clock skew - 200ps 1011 adjust x7 pll clock skew - 250ps 1100 adjust x7 pll clock skew - 300ps 1101 adjust x7 pll clock skew - 350ps 1110 adjust x7 pll clock skew - 400ps 1111 no x7pll clock skew adjustment 0x1e d[7:0] id 00000011 device identifier (max9249 = 0x03) 00000011 (read only) 0x1f d[7:4] 0000 reserved 0000 (read only) d[3:0] revision xxxx device revision (read only) max9249 gigabit multimedia serial link serializer with lvds system interface
______________________________________________________________________________________ 35 typical application circuit package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: cmos ws lflt int ms sck sd tx rx txclk+/- rxclkin+/- pclkout dout[20.0] cds int rx/sda tx/scl lock ws sck sd sd sck ws sda scl rxin0+/- to rxin2+/- cds autos rx/sda in+ in- x1 to peripherals display video-display application de vsync hsync rgb pclk clk_out out+ 45ki 45ki 1.8v 5ki 5ki 50ki 50ki lmn1 lmn0 out- tx/scl lflt int ms ws sck sd/cntlo tx0+/- to tx2+/- gpu ecu mclk uart audio max9249 max9491 max9260 max9850 package type package code outline no. land pattern no. 48 tqfp-ep c48e+8 21-0 065 90-0138 max9249 gigabit multimedia serial link serializer with lvds system interface
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 36 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 1/10 initial release 1 3/10 improved yield 2, 3 2 5/10 added soldering temperature (reflow) to the absolute maximum ratings section and corrected spread-spectrum modulation settings in table 7 2, 24 3 1/11 added patent pending to features 1 4 1/12 corrected gnd to agnd in absolute maximum ratings 2 max9249 gigabit multimedia serial link serializer with lvds system interface

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